The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having an analog/digital converter (hereinafter referred to as “ADC”) incorporated thereinto.
In recent cameras, attention has been paid to CMOS image sensors each having a CMOS device mounted therein. The CMOS image sensors are further classified into analog image sensors and digital image sensors. Although both of those image sensors have drawbacks and advantages, the digital image sensors have been increasingly expected from the viewpoints of a processing data rate.
In the recent application of the cameras, not only moving pictures can be taken, but also various applications in combination with downstream image processing have been proposed. For example, there is a case in which a close-up photo of a moment when a ball is hit on a tennis racket, or a face of a child who is passing a finishing line while running around in a playground at a school sports festival is intended to be taken. In this case, it is possible to merely point a camera at that direction to enable the camera to automatically determine a photo opportunity, and automatically press a shutter. In this application, there is a need to immediately transfer a shot image to an image processing module, and to convert photo information (analog) into image processing information (digital).
From the above background, analog/digital converters (ADC) for cameras have been already actively researched and developed. The severest problem with the CMOS image sensor resides in that data throughput is very large because information on pixels is all converted into digital information.
For example, it is assumed that one ADC executes a general moving image processing rate (30 fps) with ten million pixels. In this case, information on one pixel (for example, 4096 gray levels) is subjected to A/D conversion for 3 ns. The converted information is transferred to an output buffer. However, it is really difficult to transfer the information in a transfer time of 3 ns.
Incidentally, the invention disclosed in Japanese Patent Unexamined Application Publication No. 2008-283457 aims at enabling an effect caused by a wiring delay on a transfer line to a data output unit to be reduced, thereby taking in data on the data output unit with high precision. A column scanning circuit has a plurality of selection signal generators that output selection signals to corresponding holding circuits in synchronism with supplied drive clocks, and clock supply lines that propagate master clocks, and supply the master clocks to the selection signal generators as drive clocks. A data output circuit has a first data synchronous circuit that takes in and outputs detection data in synchronism with a first take-in clock, and a second data synchronous circuit that takes in the output data of the first data synchronous circuit in synchronism with a second take-in clock.
Also the invention disclosed in Japanese Patent Unexamined Application Publication No. 2009-130827 aims at suppressing shading appears in an output image due to differences in the amount of delay among ramp signals on the respective columns. A pixel unit includes a plurality of pixels, and outputs pixel signals to column signal lines corresponding to the respective columns. A latch circuit latches a count value of a counter until a voltage level of each ramp signal reaches a voltage level of the pixel signal as a digital pixel signal having a given bit. A controller receives the pixel signal having the given bit, and conducts correction for reducing a variation of the pixel signals after A/D conversion on the respective columns on the basis of the differences in the amount of delay among the ramp signals input to respective comparators, which are caused by the wiring lengths of the ramp signal lines.
Also, the invention disclosed in Japanese Patent Unexamined Application Publication No. 2010-166449 aims at reducing an effect caused by the wiring delay on the transfer line to the data output unit in the CMOS image sensor of a column parallel AD system. A data transfer circuit has a plurality of data output units that detect and output data transferred through respective transfer lines with a drive capability corresponding to a control signal, and a data transmitter that transfers the data to a corresponding transfer line in response to a selection signal. Further, a data transfer circuit includes a selector that outputs the selection signal to a corresponding transmitter, and a controller that controls the drive capability of the data output unit, generates the control signal for adjusting a data transfer delay, and outputs the control signal to the data output unit. The controller generates the control signal for adjusting the capability of drive according to a data transfer distance in the transfer line on the basis of the data output unit.